2-OUTPUT 3.3V PCIE CLOCK GENERATOR

2

OCTOBER 18, 2016

9FGL02 DATASHEET

Pin Configuration

SMBus Address Selection Table

Power Management Table

Power Connections

24 23 22 21 20 19

XIN/CLKIN_25 1

18 DIF1#

X2 2

17 DIF1

VDDXTAL3.3 3

16 VDDA3.3

vSADR/REF3.3 4

15 GNDA

GNDREF 5

14 DIF0#

GNDDIG 613 DIF0

78

9 10 11 12

v prefix indicates internal 120KOhm pull down resistor

9FGL02xx

ePAD is

GND

24-pin VFQFPN, 4x4 mm, 0.5mm pitch

^ prefix indicates internal 120KOhm pull up resistor

SADR

Address

0

1101000

1

1101010

State of SADR on first application

of CKPWRGD_PD#

+

Read/Write Bit

x

x

True O/P

Comp. O/P

0X

1

1

Running

Running

Running

11

Running

10

1. The output state is set by B11[1:0] (Low/Low default)

3. Input polarities defined at default values for 9FGLxx41/xx51.

4. See SMBus description for Byte 3, bit 4

2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After

this, when CKPWRG_PD# is low, REF is disabled unless

Byte3[5]=1, in which case REF is running..

CKPWRGD_PD#

SMBus

OE bit

DIF

REF

Pin Number

VDD

GND

35,24

76

11,20

10,21,25

16

15

PLL Analog

Description

XTAL, REF

Digital Power

DIF outputs