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STM32F427AI データシート(PDF) 204 Page - STMicroelectronics |
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STM32F427AI データシート(HTML) 204 Page - STMicroelectronics |
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204 / 239 page  DocID024030 Rev 9 203/238 STM32F427xx STM32F429xx Package information 231 Device marking for WLCSP143 The following figure gives an example of topside marking orientation versus ball A 1 identifier location. Other optional marking or inset/upset marks, which depends assembly location, are not indicated below. Figure 85. WLCSP143 marking example (package top view) 1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity. Table 112. WLCSP143 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 Dpad 260 µm max. (circular) 220 µm recommended Dsm 300 µm min. (for 260 µm diameter pad) PCB pad design Non-solder mask defined via underbump allowed. |
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