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STM32F413CG データシート(PDF) 124 Page - STMicroelectronics |
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STM32F413CG データシート(HTML) 124 Page - STMicroelectronics |
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124 / 207 page ![]() Electrical characteristics STM32F413xG/H 124/207 DocID029162 Rev 2 All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements for FT and TC I/Os is shown in Figure 35. Ilkg I/O input leakage current (4) VSS ≤VIN ≤VDD -- ±1 µA I/O FT/TC input leakage current (5) VIN = 5 V - - 3 RPU Weak pull-up equivalent resistor(6) All pins except for PA10 (OTG_FS_ID) VIN = VSS 30 40 50 k Ω PA10 (OTG_FS_ID) -7 10 14 RPD Weak pull-down equivalent resistor(7) All pins except for PA10 (OTG_FS_ID) VIN = VDD 30 40 50 PA10 (OTG_FS_ID) -7 10 14 CIO(8) I/O pin capacitance - - 5 - pF 1. Guaranteed by test in production. 2. Guaranteed by design. 3. With a minimum of 200 mV. 4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins, Refer to Table 57: I/O current injection susceptibility 5. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 57: I/O current injection susceptibility 6. Pull-up resistors are designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is minimum (~10% order). 7. Pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS contribution to the series resistance is minimum (~10% order). 8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization. Table 58. I/O static characteristics (continued) Symbol Parameter Conditions Min Typ Max Unit |
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