データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

STM32F413CG データシート(PDF) 128 Page - STMicroelectronics

部品番号 STM32F413CG
部品情報  ARM-Cortex-M4 32b MCUFPU, 125 DMIPS, up to 1.5MB Flash, 320KB RAM, USB OTG FS, 1 ADC, 2 DACs, 2 DFSDMs
PDF  207 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F413CG データシート(HTML) 128 Page - STMicroelectronics

Back Button STM32F413CG Datasheet HTML 124Page - STMicroelectronics STM32F413CG Datasheet HTML 125Page - STMicroelectronics STM32F413CG Datasheet HTML 126Page - STMicroelectronics STM32F413CG Datasheet HTML 127Page - STMicroelectronics STM32F413CG Datasheet HTML 128Page - STMicroelectronics STM32F413CG Datasheet HTML 129Page - STMicroelectronics STM32F413CG Datasheet HTML 130Page - STMicroelectronics STM32F413CG Datasheet HTML 131Page - STMicroelectronics STM32F413CG Datasheet HTML 132Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 128 / 207 page
background image
Electrical characteristics
STM32F413xG/H
128/207
DocID029162 Rev 2
Figure 36. I/O AC characteristics definition
6.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 58).
Unless otherwise specified, the parameters given in Table 61 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 16. Refer to Table 58: I/O static characteristics for the values of VIH and VIL for
NRST pin.
1. Guaranteed by characterization.
2. The I/O speed is configured using the OSPEEDRy[1:0] bits. Refer to the STM32F4xx reference manual for a description of
the GPIOx_SPEEDR GPIO port output speed register.
3. The maximum frequency is defined in Figure 36.
4. For maximum frequencies above 50 MHz and
VDD > 2.4 V, the compensation cell should be used.
Table 61. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RPU
Weak pull-up equivalent
resistor(1)
VIN = VSS
30
40
50
k
Ω
VF(NRST)(2) NRST Input filtered pulse
-
-
-
100
ns
VNF(NRST)(2) NRST Input not filtered pulse
VDD > 2.7 V
300
-
-
ns
TNRST_OUT Generated reset pulse duration
Internal Reset
source
20
-
-
µs
1. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum (~10% order)
.
2. Guaranteed by design.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com