LAN9211 datasheet(12/147 Pages) SMSC

12 / 147 page

High-Performance Small Form Factor Single-Chip Ethernet Controller with HP Auto-MDIX Support

Datasheet

Revision 2.9 (03-01-12)

SMSC LAN9211

DATASHEET

can control or access the TX or RX data. The MAC buffers (both TX and RX) are in effect the working

buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first to the RX

FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode

and will queue an entire frame before beginning transmission.

1.5

Receive and Transmit FIFOs

The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a

conduit between the host interface and the MAC through which all transmitted and received data and

status information is passed. Deep FIFOs allow a high degree of latency tolerance relative to the

various transport and OS software stacks thus reducing or minimizing overrun conditions. Like the

MAC, the FIFOs have separate receive and transmit data paths. In addition, the RX and TX FIFOs are

configurable in size, allowing increased flexibility.

1.6

Interrupt Controller

The LAN9211 supports a single programmable interrupt. The programmable nature of this interrupt

allows the user the ability to optimize performance dependent upon the application requirement. Both

the polarity and buffer type of the interrupt pin are configurable for the external interrupt processing.

The interrupt line can be configured as an open-drain output to facilitate the sharing of interrupts with

other devices. In addition, a programmable interrupt de-assertion interval is provided.

1.7

GPIO Interface

A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the

LAN9211. It is accessible through the host bus interface via the CSRs. The GPIO signals can function

as inputs, push-pull outputs and open drain outputs. The GPIO’s (GPO’s are not configurable) can also

be configured to trigger interrupts with programmable polarity.

1.8

Serial EEPROM Interface

A serial EEPROM interface is included in the LAN9211. The serial EEPROM is optional and can be

programmed with the LAN9211 MAC address. The LAN9211 can optionally load the MAC address

automatically after hardware reset, or soft reset.

1.9

Power Management Controls

The LAN9211 supports comprehensive array of power management modes to allow use in power

sensitive applications. Wake on LAN, Link Status Change and Magic Packet detection are supported

by the LAN9211. An external PME (Power Management Event) interrupt is provided to indicate

detection of a wakeup event.

1.10

General Purpose Timer

The general-purpose timer has no dedicated function within the LAN9211 and may be programmed to

issue a timed interrupt.

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