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ADF4356BCPZ データシート(PDF) 32 Page - Analog Devices

部品番号 ADF4356BCPZ
部品情報  6.8 GHz Wideband Synthesizer with Integrated VCO
PDF  35 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADF4356BCPZ データシート(HTML) 32 Page - Analog Devices

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ADF4356
Data Sheet
Rev. 0 | Page 32 of 35
PLL Low-Pass Filter Settling Time
The time taken for the loop to settle is inversely proportional to
the low-pass filter bandwidth. The settling time is also modeled
in the ADIsimPLL design tool.
The total lock time for changing frequencies is the sum of the
four separate times (synthesizer lock, VCO band selection, ALC
timeout, and PLL settling time) and is all modeled in the
ADIsimPLL design tool.



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