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ADGS1412 データシート(PDF) 21 Page - Analog Devices

部品番号 ADGS1412
部品情報  Serially Controlled, 1.5 廓, On-Resistance, High Voltage, iCMOS, Quad SPST Switch
PDF  26 Pages
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ホームページ  http://www.analog.com
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ADGS1412 データシート(HTML) 21 Page - Analog Devices

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ADGS1412
Data Sheet
Rev. 0 | Page 20 of 25
The ADGS1412 can only enter daisy-chain mode when in
address mode by sending the 16-bit SPI command, 0x2500
(see Figure 40). When the ADGS1412 receives this command,
the SDO of the device sends out the same command because
the alignment bits at SDO are 0x25, which allows multiple
daisy-connected devices to enter daisy-chain mode in a single
SPI frame. A hardware reset is required to exit daisy-chain mode.
For the timing diagram of a typical daisy-chain SPI frame, see
Figure 41. When CS goes high, Device 1 writes Command 0,
Bits[7:0] to its switch data register of, Device 2 writes Command 1,
Bits[7:0] to its switches, and so on. The SPI block uses the last
eight bits it received through SDI to update the switches. After
entering daisy-chain mode, the first eight bits sent out by SDO
on each device in the chain are 0x00. When CS goes high, the
internal shift register value does not reset back to zero.
An SCLK rising edge reads in data on SDI while data is
propagated out SDO on an SCLK falling edge. The expected
number of SCLK cycles must be a multiple of eight before CS
goes high. When this is not the case, the SPI interface sends the
last eight bits received to the switch data register.
POWER-ON RESET
The digital section of the ADGS1412 goes through an initialization
phase during VL power up. This initialization also occurs after a
hardware or software reset. After VL power-up or a reset, ensure
that a minimum of 120 μs from the time of power-up or reset
before any SPI command is issued. Ensure that VL does not
drop out during the 120 μs initialization phase because it may
result in incorrect operation of the ADGS1412.
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
SDO
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SDI
SCLK
CS
Figure 40. SPI Command to Enter Daisy-Chain Mode
SDO
COMMAND3[7:0]
8’h00
COMMAND2[7:0]
COMMAND3[7:0]
COMMAND1[7:0]
COMMAND2[7:0]
COMMAND0[7:0]
COMMAND1[7:0]
SDI
SDO3
8’h00
8’h00
8’h00
8’h00
COMMAND3[7:0]
8’h00
COMMAND2[7:0]
COMMAND3[7:0]
SDO2
DEVICE 2
DEVICE 1
DEVICE 4
DEVICE 3
CS
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 41. Example of a SPI Frame Where Four ADGS1412 Devices Connect in Daisy-Chain Mode



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