Functional Description

The ’97 contains six JK flip-flops connected as a synchro-

nous modulo-64 binary counter A LOW signal on the Count

Enable (CE) input permits counting with all state changes

initiated simultaneously by the rising edge of the clock

When the count reaches maximum (63) with all Qs HIGH

the Terminal Count (TC) output will be LOW if CE is LOW A

HIGH signal on Master Reset (MR) resets the flip-flops and

prevents counting although output pulses can still occur if

The flip-flop outputs are decoded by a 6-wide AND-OR-IN-

VERT gate Each AND gate also contains the buffered and

the AND gates has its other inputs HIGH The AND gates

are enabled by the counter at different times and different

rates relative to the clock For example the gate to which

S5 is connected is enabled during every other clock period

assuming S5 is HIGH Thus during one complete cycle of

the counter (64 clocks) the S5 gate is enabled 32 times and

can therefore gate 32 clocks per cycle to the output The S4

gate is enabled 16 times per cycle the S3 gate 8 times per

cycle etc The output pulse rate thus depends on the clock

rate and which of the S0 – S5 inputs is HIGH

m

64

Thus by appropriate choice of signals applied to the S0 – S5

inputs the output pulse rate can range from

to

of

the clock rate as suggested in Rate Select Table There is

no output pulse when the counter is in the ‘‘all ones’’ condi-

tion When m is 1 2 4 8 16 or 32 the output pulses are

evenly spaced assuming that the clock frequency is con-

stant For any other value of m the output pulses are not

evenly spaced since the pulse train is formed by interleav-

ing pulses passed by two or more of the AND gates The

Pulse Pattern Table indicates the output pattern for several

will be HIGH during that entire clock period while a zero

period The first column in the output field coincides with the

‘‘all zeroes’’ condition of the counter while the last column

represents the ‘‘all ones’’ condition The pulse pattern for

any particular value of m can be deduced by factoring it into

1) and combining the pulses (ie

the zeroes) shown for

1)

packages can be cascaded as shown in

Figure A Both cir-

cuits operate from the basic clock with the TC output of the

first acting to enable both counting and the output pulses of

the second package Thus the second counter advances at

only

the rate of the first and a full cycle of the two coun-

ters combined requires 4096 clocks Each rate select input

of the first package has 64 times the weight of its counter-

part in the second package

64

S1

S1

Combined output pulses are obtained in

Figure A by letting

the Z output of the first circuit act as the Y-enable function

for the second with the interleaved pulses obtained from

the Y output of the second package being opposite in phase

to the clock

TLF9780 – 3

FIGURE A Cascading for 12-Bit Rate Select

4