Data Sheet

ADA4857-1/ADA4857-2

Rev. D | Page 17 of 21

APPLICATIONS INFORMATION

POWER-DOWN OPERATION

The PD pin powers down the chip, reducing the quiescent

current and the overall power consumption. To enable the

device, pull the PD pin low. Table 8 provides the PD pin voltages

that enable the correct operation at different supplies. These

voltages are applicable for ambient temperature only. Consult

Table 1 and Table 2 when designing for use at the full operating

temperature range.

Note that PD does not put the output in a high-Z state, which

means that the ADA4857 must not be used as a multiplexer.

Table 8. PD Operation Table Guide

Supply Voltage

Condition

±5 V

±2.5 V

+5 V

Enabled

≤+0.8 V

≤−1.7 V

≤+0.8 V

Powered down

≥+3 V

≥+0.5 V

≥+3 V

CAPACITIVE LOAD CONSIDERATIONS

reduces the peaking (see Figure 54). An optimum resistor value of

40 Ω is found to maintain the peaking within 1 dB for any

capacitive load up to 40 pF.

RECOMMENDED VALUES FOR VARIOUS GAINS

Table 9 provides a useful reference for determining various gains

their contribution to the overall noise performance of the amplifier.

Gain

−3 dB SS BW (MHz)

(CSP/SOIC)

Slew Rate (V/µs),

ADA4857 Voltage

Noise (nV/√Hz), RTO

Total System

Noise (nV/√Hz), RTO

+1

0/100

0

N/A

850/750

2350

4.4

4.49

+2

0/0

499

499

360/320

1680

8.8

9.89

+5

0/0

499

124

90/89

516

22.11

23.49

+10

0/0

499

56.2

43/40

213

43.47

45.31