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MB91F467DA データシート(PDF) 116 Page - Cypress Semiconductor

部品番号 MB91F467DA
部品情報  32-bit RISC, load/store architecture, five-stage pipeline
PDF  137 Pages
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メーカー  CYPRESS [Cypress Semiconductor]
ホームページ  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

MB91F467DA データシート(HTML) 116 Page - Cypress Semiconductor

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Document Number: 002-04613 Rev. *A
Page 116 of 137
MB91460D Series
DMA transfer
(VDD35 = 4.5 V to 5.5 V, Vss5 = AVss5 = 0 V, TA = 40°C to  105°C)
Note : DREQ and DEOTX must be applied for at least 5 × tCLKT to ensure that they are really sampled and evaluated.
Under best case conditions (DMA not busy) only setup and hold times are required.
Parameter
Symbol
Pin name
Value
Unit
Min
Max
MCLKO ↓ to DACKX delay time
TCLDAL
MCLKO
DACKXn
—9
ns
TCLDAH
—
6
ns
MCLKO ↓ to DEOP delay time
TCLDEL
MCLKO
DEOPn
—8
ns
TCLDEH
—
9
ns
MCLKO ↑ to DACKX delay time
(ADDR → delayed CS)
TCHDAL
MCLKO
DACKXn
 43
ns
MCLKO ↑ to DEOP delay time
(ADDR → delayed CS)
TCHDEL
MCLKO
DEOPn
 43
ns
DREQ setup time
TDRQS
MCLKO
DREQn
23
—
ns
DREQ hold time
TDRQH
MCLKO
DREQn
0—
ns
DEOTXn setup time
TDTXS
MCLKO
DEOTXn
24
—
ns
DEOTXn hold time
TDTXH
MCLKO
DEOTXn
0—
ns



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