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AD9142ABCPZ データシート(PDF) 29 Page - Analog Devices

部品番号 AD9142ABCPZ
部品情報  Multiple chip synchronization
PDF  73 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD9142ABCPZ データシート(HTML) 29 Page - Analog Devices

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AD9142A
Data Sheet
Interface Timing Requirements
The following example shows how to calculate the optimal
delay at the data source to achieve the best sampling timing in
the delay line interface mode:
•
fDCI = 200 MHz
•
Delay setting = 0
The shadow area in Figure 38 is the interface setup and hold
time window set to 0. To optimize the interface timing, this
window must be placed in the middle of the data transitions.
Because the input is double data rate, the available data period
is 2.5 ns. Therefore, the optimal data bus delay, with respect to
the DCI at the data source, can be calculated as
ns
13
.
0
25
.
1
38
.
1
2
2
|)
|
|
(|
=
−
=
−
+
=
PERIOD
DATA
H
S
DELAY
t
t
t
t
SPI Sequence to Enable Delay Line Interface Mode
Use the following SPI sequence to enable the delay line interface
mode:
1.
0x5E → 0x00 /* Configure the delay
setting */
2.
0x5F → 0x60
3.
0x0D → 0x16 /* DC couple DCI */
4.
0x0A → 0x00 /* Turn off DLL and duty
cycle correction */
Rev. A | Page 28 of 72



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