WM8198

Production Data

w

PD Rev 4.0 June 2004

22

OPERATING MODE TIMING DIAGRAMS

The following diagrams show 8-bit multiplexed output data and MCLK, VSMP and input video

requirements for operation of the most commonly used modes as shown in Table 4. The diagrams

are identical for both CDS and non-CDS operation. Outputs from RINP, GINP and BINP are shown

as R, G and B respectively. X denotes invalid data.

MCLK

VSMP

INPUT VIDEO

OP[7:0]

(DEL = 00)

16.5 MCLK PERIODS

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

R

A

R

B

G

A

G

B

B

A

B

B

OP[7:0]

(DEL = 01)

B

A

B

B

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

G

A

G

B

B

A

B

B

B

A

B

B

R

A

R

B

G

A

G

B

OP[7:0]

(DEL = 10)

G

A

G

B

B

A

B

B

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

G

A

G

B

G

A

G

B

B

A

B

B

R

A

R

B

OP[7:0]

(DEL = 11)

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

G

A

G

B

B

A

B

B

R

A

R

B

G

B

G

A

B

A

B

B

R

A

R

B

R

A

R

B

G

A

G

B

B

A

B

B

B

A

B

B

G

A

G

B

B

A

B

B

R

A

R

B

R

A

R

B

G

A

G

B

G

A

G

B

B

A

B

B

Figure 18 Mode 1 Operation

Figure 19 Mode 2 Operation