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ZOPT2202AC5R データシート(PDF) 22 Page - Integrated Device Technology |
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ZOPT2202AC5R データシート(HTML) 22 Page - Integrated Device Technology |
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22 / 41 page ![]() ZOPT2202 Datasheet © 2016 Integrated Device Technology, Inc 22 September 21, 2016 3.8.4 I²C Interface—Bus Timing Figure 3.7 Bus Timing Table 3.9 Bus Timing Characteristic PARAMETER SYMBOL Standard Mode Fast Mode UNITS Maximum SCL clock frequency fSCL 100 400 kHz Minimum START condition hold time relative to SCL edge tHDSTA 4 s Minimum SCL clock low width tLOW 4.7 s Minimum SCL clock high width tHIGH 4 s Minimum START condition setup time relative to SCL edge tSUSTA 4.7 s Minimum data hold time on SDA relative to SCL edge tHDDAT 0 s Minimum data setup time on SDA relative to SCL edge tSUDAT 0.1 0.1 s Minimum STOP condition setup time on SCL tSUSTO 4 s Minimum bus free time between stop condition and start condition tBUS 4.7 s SDA SCL tHDSTA tLOW tHDDAT tSUDAT tHIGH tSUSTA tHDSTA tSUSTO tBUS |
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