PC33888APNB datasheet(21/32 Pages) MOTOROLA

21 / 32 page

MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA

33888

Device Register Addressing

The following section describes the possible register

addresses and their impact on device operation.

Address 000—SPI Output Control Register (SOCR)

The SOCR register allows the MCU to control the outputs via

the SPI. Incoming message bits D3:D0 reflect the desired

states of high-side outputs HS3:HS0. Message bits D11:D4

reflect the desired state of low-side outputs LS11:LS4,

respectively.

Address 100—Direct Input Control Register (DICR)

The DICR register is used by the MCU to enable direct input

control of the outputs. For the outputs, a logic [0] on bits D11:D0

will enable the corresponding output for direct control. A

logic [1] on a D11:D0 bit will disable the output from direct

control.

Address 010—Logic Function Control Register (LFCR)

The LFCR register is used by the MCU to configure the

relationship between SOCR bits D11:D0 and the direct inputs

IHS[0:3] and ILS. While addressing this register (if the direct

inputs were enabled for direct control with the DICR), a logic [1]

on any or all of the D3:D0 bits will result in a Boolean AND of

the IHS[0:3] terminal(s) with its (their) corresponding D3:D0

message bit(s) when addressing the SOCR. A logic [1] on any

or all of the D11:D4 bits will result in a Boolean AND of the ILS

and the corresponding D11:D4 message bits when addressing

the SOCR. Similarly, a logic [0] on the D3:D0 bits will result in

a Boolean OR of the IHS[0:3] terminal(s) with their

corresponding message bits when addressing the SOCR

D11:D4 when addressing the SOCR register (if ILS is enabled).

Table 2. SI Message Bit Assignment

Bit Sig

SI Msg Bit

Message Bit Description

MSB

D15

Watchdog in: toggled to satisfy watchdog

requirements.

D14:12

D11

Used to configure Low-Side Output LS11.

D10

Used to configure Low-Side Output LS10.

Used to configure Low-Side Output LS9.

Used to configure Low-Side Output LS8.

Used to configure Low-Side Output LS7.

Used to configure Low-Side Output LS6.

Bit Sig

SI Msg Bit

Message Bit Description

Used to configure Low-Side Output LS5

(Watchdog timeout MSB during WDCSCR

configuration).

Used to configure Low-Side Output LS4

(Watchdog timeout LSB during WDCSCR

configuration).

Used to configure High-Side Output HS3.

Used to configure High-Side Output HS2.

Used to configure High-Side Output HS1.

LSB

Used to configure High-Side Output HS0.

Table 2. SI Message Bit Assignment (continued)

Table 3. Serial Input Address and Configuration Bit Map

Address

Low-Side

High-Side

D15

D14

D13

D12

D11

D10

SOCR

LS11

LS10

LS9

LS8

LS7

LS6

LS5

LS4

HS3

HS2

HS1

HS0

DICR

PWB11 PWB10 PWB9 PWB8 PWB7 PWB6 PWB5 PWB4 PWB3 PWB2

PWB1

PWB0

LFCR

A/OB11 A/OB10 A/OB9 A/OB8 A/OB7 A/OB6 A/OB5 A/OB4 A/OB3 A/OB2 A/OB1 A/OB0

WDCSCR

WDH

WDL

CS3

CS2

CS1

CS0

OLCR

OL11

OL10

OL9

OL8

OL7

OL6

OL5

OL4

OLB3

OLB2

OLB1

OLB0

CLOCCR

OC11

OC10

OC9

OC8

OC7

OC6

OC5

OC4

ILIM3

ILIM2

ILIM1

ILIM0

NOT

USED

–

TEST

–

ILIMPK

ILIM

x=Don’t care.

NA=Not applicable.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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