LM98501CCVBH datasheet(21/24 Pages) NSC

21 / 24 page

PGA Gain Plots

Applications Information

ANALOG-TO-DIGITAL CONVERTER REFERENCE

BYPASSING

Figure 17 shows a simple reference bypassing scheme with

minimal components. The V

REFT and VREFB pins should

each be bypassed to analog ground with 10 µF tantalum as

well as 0.1 µF ceramic capacitors. In a case where the inter-

nally generated reference voltages are not sufficient, the

user may supply external voltages to the reference pins.

However, the reference pin V

REFT should be within the range

of 2.0V to 2.5V. Similarly, V

REFB should be driven in the

range of 0.4V to 0.9V. Any device used to drive the reference

pins should be able to source adequate current into the

REFT and sink adequate current from the VREFB pin when

the reference resistor ladder is at its minimum resistivity of

850

Ω.

The reference voltage at the top of the resistor ladder

REFT) may be as low as 1.2V above the voltage at the bot-

tom of the resistor ladder (V

REFB) and may be as high as

1.8V above. V

REFB may be as low as 0.4V and as high as

0.9V above ground. However, noise effects will be minimized

and accurate conversions insured when the total reference

voltage is approximately 2.25V and offset from ground by

0.75V.

ANALOG OFFSET DAC REFERENCE BYPASSING

The analog offset DAC reference pins, VREFP and VREFN,

should be capacitively bypassed in the same fashion as the

ADC

reference

pins

VREFT

and

VREFB

(see

’Analog-to-Digital Converter Reference Bypassing’).

DS101292-14

FIGURE 15. PGA Gain (Linear Scale) vs. PGA Gain Code

DS101292-15

FIGURE 16. PGA Gain (Logarithmic Scale) vs. PGA Gain Code

DS101292-16

FIGURE 17. Reference Bypassing

LM98501CCVBH データシート(PDF) 21 Page - National Semiconductor (TI)

LM98501CCVBH データシート(HTML) 21 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

データシートダウンロード