GL816 – USB 2.0 Flash Card Reader Controller

©2000-2001 Genesys Logic Inc.—All rights reserved.

Page 7

3.2 Functional Overview

3.2.1 UTM

The USB 2.0 Transceiver Macrocell, it’s the analog circuitry that handles the low

level USB protocol and signaling, and shifts the clock domain of the data from the

USB 2.0 rate to one that is compatible with the general logic.

3.2.2 SIE

The Serial Interface Engine, which contains the USB PID and address recognition

logic, and other sequencing and state machine logic to handle USB packets and

transactions.

3.2.3 EP0 FIFO

It is composed of TX0FIFO and RX0FIFO, with 64-byte FIFO each, and it is used for

endpoint 0 data transfer.

3.2.4 EP3 FIFO

It’s an 8-byte FIFO for endpoint 3.

3.2.5 Bulk FIFO

It is composed of TXFIFO and RXFIFO for data transmission and receiving

respectively, also with different modes support:

3.2.5.1 TXFIFO:

1. To ensure the continuous data transmission, TXFIFO includes 512 bytes

DATA-A FIFO, 512 bytes DATA-B FIFO, and two 16 bytes corresponding

redundant areas. All can be directly accessed by 8051 µC.

2. Normally SIE popes data, MHE pushes data for DATA A/B FIFOs, and

redundant area is pushed by MHE when SmartMedia MIF is enabled and

popped by uC.

3. Supports uC single byte access for SmartMedia ECC error correction.

4. At transmit mode SIE won’t transmit data filled in TXFIFO before uC complete

the data integrity checking.

3.2.5.2 RXFIFO:

1. To ensure the continuous data transmission, RXFIFO includes 512 bytes

DATA-A FIFO, 512 bytes DATA-B FIFO, and 16 bytes single redundant area. All

can be directly accessed by 8051 µC.