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MN39160FH データシート(PDF) 2 Page - Panasonic Semiconductor |
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MN39160FH データシート(HTML) 2 Page - Panasonic Semiconductor |
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2 / 9 page ![]() MN39160FH 2 SMD00002BEC ■ Block Diagram Pin No. Symbol Description 8 VO Video output 9 GND GND 10 φ R Reset pulse (RG) 11 φ H1 Horizontal register clock pulse 1 12 φ H2 Horizontal register clock pulse 2 13 Sub Substrate 14 PT P-well for protection circuit Pin No. Symbol Description 1 φ V4 Vertical shift register clock pulse 4 2 φ V3 Vertical shift register clock pulse 3 3 φ V2 Vertical shift register clock pulse 2 4 φ V1 Vertical shift register clock pulse 1 5 GND GND 6 TEST TEST pin (OPEN) * 1 7VDD Power supply ■ Pin Descriptions ■ Device Parameter (H × V) Note) *1: TEST pin must be left open, because the pin outputs CCD internal bias volltage. Photo diode 8 13 7 9 1 φ V4 φV3 φV2 φV1 GND TEST *1 2 3 4 5 PT 14 6 Sub VO VDD GND Horizontal register (one dummy at the front, no dummy at the back) *1 : TEST pin must be left open, because the pin outputs CCD internal bias voltage. (4 columns OB + 962 columns valid area + 41 columns OB) Parameter Value Unit Pixel number * 1 962 × 654 pixel Image sensing block dimension 3.655 6 × 2.714 1mm2 Pixel dimension 3.80 × 4.15 µm2 Note) *1: OB columns are not included. |
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