IOBUS0 datasheet(50/88 Pages) FTDI

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Datasheet

Vinculum-II Embedded Dual USB Host Controller IC

V ers ion 1 .7

Doc ument N o.: FT _000138 C learance N o.: FT DI# 1 43

The VNC2 SPI interface uses 4 signal lines: SCLK, SS, MOSI and MISO. The signals MOSI, MISO and SS

are always clocked on the rising edge of the SCLK signal.

SS signal must be raised high for the duration of the entire transaction. For data transactions, the SS

must be released for at least one clock cycle after a transaction has completed. It is not necessary to

release SS between Status Read operations.

The ‘Start’ state of MOSI and SS high on the rising edge of SCLK initiates the transfer. The transfer

finishes after 13 clock cycles, and the next transfer starts when MOSI is high during the rising edge of

CLK.

The following Figure 6.16 and

Table 6.9 give details of the bus timing requirements.

Figure 6.16 SPI Slave Mode Timing

Table 6.9 SPI Slave Data Timing

6.3.6.2 SPI Master Data Read Transaction in VNC1L legacy mode

The SPI master must periodically poll for new data in VNC2 Transmit Buffer. It is recommended that this

is done first before sending any command.

The Start and Setup sequence is sent to VNC2 by the SPI master, see Figure 6.17.

The VNC2 clocks out data from its Transmit Buffer on subsequent rising edge clock cycles provided by the

SPI master. This is followed by a status bit generated by VNC2. The Data Read status bit is defined in

Table 6.10.

If the status bit indicates New Data then the byte received is valid. If it indicates Old Data then the

Transmit Buffer in VNC2 is empty and the byte of data received in the current transaction should be

disregarded.

Time

Description

Minimum

Typical

Maximum

Unit

SCLK period

79.37

83.33

SCLK high period

39.68

41.67

39.68

SCLK low period

39.68

41.67

39.68

SCLK driving edge to

MISO/MOSI

0.5

MISO/SS setup time to sample

SCLK edge

MISO/SS hold time from sample

SCLK edge

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