Figure 4 shows the input data format A start bit of logical

‘‘1’’ precedes the 32 bits of data At the 36th clock a LOAD

signal is generated synchronously with the high state of the

clock which loads the 32 bits of the shift registers into the

latches At the low state of the clock a RESET signal is

generated which clears all the shift registers for the next set

of data The shift registers are static master-slave configura-

tion There is no clear for the master portion of the first shift

register thus allowing continuous operation

If the clock is not continuous there must be a complete set

of 36 clocks otherwise the shift registers will not clear

Figure 2a shows the pin-out of the MM5452 Bit 1 is the first

bit following the start bit and it will appear on pin 18

Figure 3 shows the timing relationships between data clock

and DATA ENABLE

TLF6137 – 4

FIGURE 3

TLF6137 – 5

FIGURE 4 Input Data Format

4