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NS32FX161-15 データシート(PDF) 2 Page - National Semiconductor (TI) |
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NS32FX161-15 データシート(HTML) 2 Page - National Semiconductor (TI) |
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2 / 102 page  Table of Contents 10 PRODUCT INTRODUCTION 6 11 NS32FX164 Special Features 6 20 ARCHITECTURAL DESCRIPTION 7 21 Register Set 7 211 General Purpose Registers 7 212 Address Registers 8 213 Processor Status Register 8 214 Configuration Register 9 215 DSP Module Registers 9 22 Memory Organization 11 221 Address Mapping 12 23 Modular Software Support 12 24 Instruction Set 12 241 General Instruction Format 12 242 Addressing Modes 14 243 Instruction Set Summary 16 25 Graphics Support 20 251 Frame Buffer Addressing 20 252 BITBLT Fundamentals 20 2521 Frame Buffer Architecture 21 2522 Bit Alignment 21 2523 Block Boundaries and Destination Masks 21 2524 BITBLT Directions 22 2525 BITBLT Variations 23 253 Graphics Support Instructions 23 2531 BITBLT (BIT-aligned BLock Transfer) 23 2532 Pattern Fill 24 2533 Data Compression Expansion and Magnify24 25331 Magnifying Compressed Data 26 30 FUNCTIONAL DESCRIPTION 26 31 Instruction Execution 26 311 Operating States 26 312 Instruction Endings 26 3121 Completed Instructions 27 3122 Suspended Instructions 27 3123 Terminated Instructions 27 3124 Partially Completed Instructions 27 313 Slave Processor Instructions 27 3131 Slave Processor Protocol 27 3132 Floating-Point Instructions 28 32 Exception Processing 29 321 Exception Acknowledge Sequence 29 322 Returning from an Exception Service Procedure 30 323 Maskable Interrupts34 3231 Non-Vectored Mode 34 3232 Vectored Mode Non-Cascaded Case 35 3233 Vectored Mode Cascaded Case 35 324 Non-Maskable Interrupt 37 325 Traps 37 326 Priority among Exceptions 37 327 Exception Acknowledge Sequences Detailed Flow 39 3271 MaskableNon-Maskable Interrupt Sequence 39 3272 SLAVEILLSVCDVZFLGBPTUND Trap Sequence 39 3273 Trace Trap Sequence 39 33 Debugging Support 40 331 Instruction Tracing 40 34 DSP Module 40 341 Programming Model 40 342 RAM Organization and Data Types 41 3421 Integer Values 41 3422 Aligned-Integer Values 41 3423 Real Values 41 3434 Aligned-Real Values 41 3425 Extended Precision Real Values 41 3426 Complex Values 42 343 Command List Format 42 344 CPU Core Interface 42 3441 Synchronization of Parallel Operation 42 3442 DSPM RAM Organization 43 345 DSPM Instruction Set 43 3451 Conventions 43 3452 Type Casting 43 3453 General Notes 44 3454 Load Register Instructions 44 3455 Store Register Instructions 45 3456 Adjust Register Instructions 46 3457 Flow Control Instructions 47 3458 Internal Memory Move Instructions 48 3459 External Memory Move Instructions 48 34510 ArithmeticLogical Instructions 49 34511 Multiply-and-Accumulate Instructions 49 34512 Multiply-and-Add Instructions 50 34513 Clipping and MinMax Instructions 52 34514 Special Instructions 53 2 |
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