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STM32F411CC データシート(PDF) 63 Page - STMicroelectronics |
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STM32F411CC データシート(HTML) 63 Page - STMicroelectronics |
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63 / 149 page ![]() DocID026289 Rev 6 63/149 STM32F411xC STM32F411xE Electrical characteristics 123 PD Power dissipation at TA = 125 °C (range 3)(7) UFQFPN48 - - 156 mW WLCSP49 - - 98 LQFP64 - - 106 LQFP100 - - 116 UFBGA100 - - 81 TA Ambient temperature for range 6 Maximum power dissipation - 40 - 85 °C Low power dissipation(8) - 40 - 105 Ambient temperature for range 7 Maximum power dissipation - 40 - 105 Low power dissipation(8) - 40 - 125 Ambient temperature for range 3 Maximum power dissipation - 40 - 110 Low power dissipation(8) - 40 - 130 TJ Junction temperature range Range 6 - 40 - 105 Range 7 - 40 - 125 Range 3 - 40 - 130 1. VDD/VDDA minimum value of 1.7 V with the use of an external power supply supervisor (refer to Section 3.15.2: Internal reset OFF). 2. When the ADC is used, refer to Table 65: ADC characteristics. 3. If VREF+ pin is present, it must respect the following condition: VDDA-VREF+ < 1.2 V. 4. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and power-down operation. 5. Guaranteed by test in production. 6. To sustain a voltage higher than VDD+0.3, the internal Pull-up and Pull-Down resistors must be disabled 7. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax. 8. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax. Table 14. General operating conditions (continued) Symbol Parameter Conditions Min Typ Max Unit Table 15. Features depending on the operating power supply range Operating power supply range ADC operation Maximum Flash memory access frequency with no wait states (fFlashmax) Maximum Flash memory access frequency with wait states (1)(2) I/O operation Clock output frequency on I/O pins(3) Possible Flash memory operations VDD =1.7 to 2.1 V(4) Conversion time up to 1.2 Msps 16 MHz(5) 100 MHz with 6 wait states – No I/O compensation up to 30 MHz 8-bit erase and program operations only VDD = 2.1 to 2.4 V Conversion time up to 1.2 Msps 18 MHz 100 MHz with 5 wait states – No I/O compensation up to 30 MHz 16-bit erase and program operations |
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