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STM32F411RET6 データシート(PDF) 107 Page - STMicroelectronics

部品番号 STM32F411RET6
部品情報  ARM® Cortex®-M4 32b MCUFPU, 125 DMIPS, 512KB Flash, 128KB RAM, USB OTG FS, 11 TIMs, 1 ADC, 13 comm. interfaces
PDF  149 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32F411RET6 データシート(HTML) 107 Page - STMicroelectronics

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DocID026289 Rev 6
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STM32F411xC STM32F411xE
Electrical characteristics
123
SPI interface characteristics
Unless otherwise specified, the parameters given in Table 60 for the SPI interface are
derived from tests performed under the ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 14, with the following configuration:
Output speed is set to OSPEEDRy[1:0] = 10
Capacitive load C = 30 pF
Measurement points are done at CMOS levels: 0.5VDD
Refer to Section 6.3.16: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 60. SPI dynamic characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master full duplex/receiver mode,
2.7 V < VDD < 3.6 V
SPI1/4/5
--
42
MHz
Master full duplex/receiver mode,
3.0 V < VDD < 3.6 V
SPI1/4/5
--
50
Master transmitter mode
1.7 V < VDD < 3.6 V
SPI1/4/5
--
50
Master mode
1.7 V < VDD < 3.6 V
SPI1/2/3/4/5
--
25
Slave transmitter/full duplex mode
2.7 V < VDD < 3.6 V
SPI1/4/5
--
38(2)
Slave receiver mode,
1.8 V < VDD < 3.6 V
SPI1/4/5
--
50
Slave mode,
1.8 V < VDD < 3.6 V
SPI1/2/3/4/5
--
25
Duty(SCK)
Duty cycle of SPI clock
frequency
Slave mode
30
50
70
%
tw(SCKH)
tw(SCKL)
SCK high and low time Master mode, SPI presc = 2
TPCLK−1.5
TPCLK
TPCLK
+1.5
ns
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
3TPCLK
--
ns
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2TPCLK
--
ns
tsu(MI)
Data input setup time
Master mode
4
-
-
ns
tsu(SI)
Slave mode
2.5
-
-
ns
th(MI)
Data input hold time
Master mode
7.5
-
-
ns
th(SI)
Slave mode
3.5
-
-
ns



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