PC87307 datasheet(39/218 Pages) NSC

39 / 218 page

Configuration

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2.10 PROGRAMMABLE CHIP SELECT

CONFIGURATION REGISTERS

The chip select configuration registers are accessed using

two index levels. The first index level accesses the Pro-

grammable Chip Select Index register at 23h. See Section

2.4.5 on page 35. The second index level accesses a spe-

cific chip select configuration register as shown in Table

2-22.

See also, “Programmable Chip Select Output Signals” on

page 171 and the description of each signal in Table 1-1 on

page 15.

TABLE 2-22. The Programmable Chip Select

Conﬁguration Registers

2.10.1

CS0 Base Address MSB, Second Level

Index 00h

This read/write register is reset by hardware to 00h. Same

as Plug and Play ISA base address register at index 60h.

See Table 2-7 on page 28.

2.10.2

CS0 Base Address LSB Register, Second Level

Index 01h

This read/write register is reset by hardware to 00h. It is the

same as the Plug and Play ISA base address register at in-

dex 61h. See Table 2-7 on page 28.

2.10.3

CS0 Configuration Register, Second Level

Index 02h

This read/write register is reset by hardware to 00h. It con-

trols activation of the CS0 signal upon an address match,

when AEN is inactive (low) and the non-masked address

pins match the corresponding base address bits.

Second

Level

Index

Type Reset

00h

CS0 Base Address MSB Register R/W

00h

01h

CS0 Base Address LSB Register R/W

00h

02h

CS0 Conﬁguration Register

R/W

00h

03h

Reserved

04h

CS1 Base Address MSB Register R/W

00h

05h

CS1 Base Address LSB Register R/W

00h

06h

CS1 Conﬁguration Register

R/W

00h

07h

Reserved

08h

CS2 Base Address MSB Register R/W

00h

09h

CS2 Base Address LSB Register R/W

00h

0Ah

CS2 Conﬁguration Register

R/W

00h

0Bh-0Fh

Reserved

10h-FFh

Not Accessible

FIGURE 2-14. CS0 Conﬁguration Register Bitmap

Bit 0 - Mask Address Pin A0

0 - A0 is decoded.

1 - A0 is not decoded; it is ignored.

Bit 1 - Mask Address Pin A1

0 - A1 is decoded.

1 - A1 is not decoded (ignored).

Bit 2 - Mask Address Pin A2

0 - A2 is decoded.

1 - A2 is not decoded; it is ignored.

Bit 3 - Mask Address Pin A3

0 - A3 is decoded.

1 - A3 is not decoded; it is ignored.

Bit 4 - Assert Chip Select Signal on Write

0 - Chip select not asserted on address match and

when WR is active (low).

1 - Chip select asserted on address match and when

WR is active (low).

Bit 5 - Assert Chip Select Signal on Read

0 - Chip select not asserted on address match and

when RD is active (low).

1 - Chip select asserted on address match and when

RD is active (low).

Bit 6 - Unaffected by RD/WR

Bits 5 and 4 are ignored when this bit is set.

0 - Chip select asserted on address match, qualiﬁed by

RD or WR pin state and contents of bits 5 and 4.

1 - Chip select asserted on address match, regardless

of RD or WR pin state and regardless of contents

of bits 5 and 4.

Bit 7 - Mask Address Pins A11-A0

0 - A11-A0 are decoded.

1 - A11-A0 are not decoded; they are ignored.

2.10.4

Reserved, Second Level Index 03h

Attempts to access this register produce undefined results.

Mask Address Pins A11-A0

76543210

Reset

Required

Second Level

Mask Address Pin A3

CS0 Configuration

Mask Address Pin A1

Mask Address Pin A2

Assert Chip Select Signal on Read

Mask Address Pin A0

Unaffected by RD/WR

Assert Chip Select Signal on Write

Index 02h

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