PC87366 datasheet(78/240 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.19 GAME PORT (GMP) CONFIGURATION

2.19.1

Logical Device 11 (GMP) Configuration

Table 34 lists the configuration registers which affect the Game Port. Only the last register (F0h) is described here. See Sec-

tions 2.2.3 and 2.2.4 for a detailed description of the others.

Table 34. GMP Conﬁguration Registers

2.19.2

Game Port Configuration Register

This register is reset by hardware to 00h.

Location:

Index F0h

Type:

R/W

Usage Hint:

To operate GMP enhanced features, make sure to locate its base address within the LPC Wide Generic address range.

Index

Conﬁguration Register or Action

Type

Reset

30h

Activate. When bit 0 is cleared, the registers of this logical device are not

accessible.

R/W

00h

60h

Base Address MSB register

R/W

02h

61h

Base Address LSB register. Bits 3-0 (for A3-A0) are read only, 0000b.

R/W

00h

70h

Interrupt Number and Wake-Up on IRQ Enable register.

R/W

00h

71h

Interrupt Type. Bit 1 is read/write. Other bits are read only.

R/W

03h

74h

Report no DMA assignment

04h

75h

Report no DMA assignment

04h

F0h

Game Port Conﬁguration register

R/W

00h

Bit

76543210

Name

Reserved

Internal

Pull-Up

Enable

Reserved

Reset

00000000

Bit

Description

7-3

Reserved

Internal Pull-Up Enable. When the GMP functions are selected, this bit controls the internal pull-up resistor on

pins 119 (GPIO22/JOYABTN0), 120 (GPIO23/JOYABTN1), 123 (GPIO26/JOYBBTN0) and 124

(GPIO27/JOYBBTN1).

0: Disabled (default)

1: Enabled

1-0

Reserved

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