L99MD02 datasheet(25/46 Pages) STMICROELECTRONICS

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L99MD02

Functional description of the SPI

Doc ID 16082 Rev 5

25/46

The data returned on SDO within the same frame always starts with the <Global Status>

‘In-frame-response’, Figure 8).

For write cycles the <Global Status> register is followed by the previous content of the

addressed register.

For read cycles the <Global Status> register is followed by the content of the addressed

6.2.2

Command byte

Each communication frame starts with a command byte. It consists of an operating code

which specifies the type of operation (<Read>, <Write>, <Read and Clear Status>, <Read

Device Information>) and a 6 bit address.

The <Write Mode> and <Read Mode> operations allow access to the RAM of the device,

i.e. write to control registers or read status information.

A <Read and Clear Status> Operation addressed to a device specific status register will

read back and subsequently clear this status register. A <Read and Clear Status> Operation

with address 3FH clears all status registers at a time and reads back the <Configuration>

A <Read and Clear Status> operation addressed to an unused RAM address register will be

identical to a <Read Mode> operation (in case of unused RAM address, the second byte will

be equal to 00H).

<Read Device Information> allows access to the ROM area which contains device related

information such as the product family, product name, silicon version and register width.

Table 17.

Command byte (8 bit)

Operating code

Address

Bit

Name

OC1

OC0

Table 18.

Data byte

Data Byte 1

Data Byte 0

Bit

Name

D15

D14

D13

D12

D11

D10

Table 19.

Operating code definition

OC1

OC0

Meaning

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