VSC7212RG datasheet(21/34 Pages) VITESSE

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VITESSE

SEMICONDUCTOR CORPORATION

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC7212

Gigabit Interconnect Chip

G52268-0, Rev 3.3

Page 21

04/10/01

Tel: (800)-VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Figure 15: Transmit Input Timing Waveforms with TMODE = 11X (“ASIC-Friendly” Timing)

Table 10: Transmit Input AC Characteristics with TMODE = 11X

Figure 16: Transmit Serial Timing Waveforms

Table 11: Transmit Serial AC Characteristics

Parameters

Description

Min

Max

Units

Conditions

Input Skew relative to the rising

edge of TBC

—

2.0

Measured between the valid data

level of the input and the 1.4V point

of TBC

Parameters

Description

Min

Max

Units

Conditions

TSDR, TSDF

TX+/- rise and fall time

—

330

Between VOL(MAX) and

VOH(MIN)

TLAT

Latency, REFCLK to TX0

Latency, TBC to TX0

22bc+0.2ns

36bc+0.0ns

22bc+0.8ns

38bc+0.3ns

bc + ns

ENDEC=1 TMODE=000

ENDEC=1 TMODE=10X

Serial data output

Total Jitter (p-p)

—

192

IEEE 802.3z Clause 38.69,

Tested on a sample basis

TDJ

Serial data output

Deterministic Jitter (p-p)

—

IEEE 802.3z Clause 38.69,

Tested on a sample basis

Valid

Internal Clock

(from PLL)

TBC

T(7:0)

C/D

WSEN

TSDR, TSDF

TLAT

TX+, TX-

TX0

Internal Clock

(from PLL)

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