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SPC560P50L5 データシート(PDF) 28 Page - STMicroelectronics |
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SPC560P50L5 データシート(HTML) 28 Page - STMicroelectronics |
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28 / 112 page  Introduction SPC560P44Lx, SPC560P50Lx 28/112 Doc ID 14723 Rev 9 The JTAG controller provides the following features: ● IEEE Test Access Port (TAP) interface with 4 pins (TDI, TMS, TCK, TDO) ● Selectable modes of operation include JTAGC/debug or normal system operation. ● A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions: – BYPASS, IDCODE, EXTEST, SAMPLE, SAMPLE/PRELOAD ● A 5-bit instruction register that supports the additional following public instructions: – ACCESS_AUX_TAP_NPC, ACCESS_AUX_TAP_ONCE ● 3 test data registers: a bypass register, a boundary scan register, and a device identification register. ● A TAP controller state machine that controls the operation of the data registers, instruction register and associated circuitry. 1.5.32 On-chip voltage regulator (VREG) The on-chip voltage regulator module provides the following features: ● Uses external NPN (negative-positive-negative) transistor ● Regulates external 3.3 V /5.0 V down to 1.2 V for the core logic ● Low voltage detection on the internal 1.2 V and I/O voltage 3.3 V |
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