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ST7FOXU0 データシート(PDF) 45 Page - STMicroelectronics |
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ST7FOXU0 データシート(HTML) 45 Page - STMicroelectronics |
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45 / 123 page  ST7FOXU0 Interrupts 45/123 7.3.1 External Interrupt Control Register 1 (EICR1) Reset value: 0000 0000 (00h) Bits 7:6 = Reserved, must be kept cleared. Bits 5:4 = IS2[1:0] ei2 sensitivity bits These bits define the interrupt sensitivity for ei2 according to Table ?. Bits 3:2 = IS1[1:0] ei1 sensitivity bits These bits define the interrupt sensitivity for ei1 according to Table ?. Bits 1:0 = IS0[1:0] ei0 sensitivity bits These bits define the interrupt sensitivity for ei0 according to Table ?. Note: 1 These 8 bits can be written only when the I bit in the CC register is set. 2 Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. Refer to Section : External interrupt function. 3 Whatever the sensitivity configuration, ei2 cannot exit the MCU from HALT, ACTIVE-HALt and AWUFH modes when a falling edge occurs. 7 0 0 0 IS21 IS20 IS11 IS10 IS01 IS00 Read/write ISx1 ISx0 External interrupt sensitivity 0 0 Falling edge & low level 0 1 Rising edge only 1 0 Falling edge only 1 1 Rising and falling edge |
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