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ST7LITEUS2 データシート(PDF) 35 Page - STMicroelectronics |
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ST7LITEUS2 データシート(HTML) 35 Page - STMicroelectronics |
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35 / 136 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) ST7LITEUS2, ST7LITEUS5 Supply, reset and clock management 35/136 6.4 Reset sequence manager (RSM) 6.4.1 Introduction The reset sequence manager includes three reset sources as shown in Figure 12: ● External RESET source pulse ● Internal LVD reset (low voltage detection) ● Internal WATCHDOG reset Note: A reset can also be triggered following the detection of an illegal opcode or prebyte code. Refer to Figure 12. These sources act on the RESET pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory map. The basic reset sequence consists of 3 phases as shown in Figure 11: ● Active phase depending on the reset source ● 64 CPU clock cycle delay ● RESET vector fetch Caution: When the ST7 is unprogrammed or fully erased, the Flash is blank and the RESET vector is not programmed. For this reason, it is recommended to keep the RESET pin in low state until programming mode is entered, in order to avoid unwanted behavior. The 64 CPU clock cycle delay allows the oscillator to stabilise and ensures that recovery has taken place from the Reset state. The RESET vector fetch phase duration is 2 clock cycles. Figure 11. Reset sequence phases RESET Active phase INTERNAL RESET 64 CLOCK CYCLES FETCH VECTOR Obsolete Product(s) - Obsolete Product(s) |
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