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ST10F296 データシート(PDF) 156 Page - STMicroelectronics |
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ST10F296 データシート(HTML) 156 Page - STMicroelectronics |
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156 / 346 page  Obsolete Product(s) - Obsolete Product(s) Parallel ports ST10F296E 156/346 Note: The open-drain output option can only be selected via software during the initialization routine. The CS0 signal is in push-pull output driver mode directly after reset (see Figure 50 on page 156). The bus arbitration signals HOLD, HLDA and BREQ are selected with the HLDEN bit in the PSW register. When the bus arbitration signals are enabled via HLDEN, these pins are switched automatically to the appropriate direction. The pin drivers for HLDA and BREQ are automatically enabled while the pin driver for HOLD is automatically disabled (see Figure 51 on page 157 and Figure 52 on page 158). Figure 50. Block diagram of Port 6 pins 7, 6, 1, 0 MUX 0 1 0 Open-drain latch Write ODP6.y Read ODP6.y Direction latch Write DP6.y Read DP6.y MUX 0 1 Input latch Clock P6.y Output buffer y = (7, 6, 1, 0) Port output latch Read P6.y Write P6.y Alternate data output MUX 0 1 MUX 0 1 1 MUX Alternate function enable Obsolete Product(s) - Obsolete Product(s) |
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