ST10F296 datasheet(214/346 Pages) STMICROELECTRONICS

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System reset

ST10F296E

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System reset

System reset initializes the MCU in a predefined state. There are six ways to activate a reset

state. The system start-up configuration is different for each case as shown in Table 131

20.1

Input filter

On the RSTIN input pin, an on-chip RC filter is implemented. It is sized to filter all the spikes

shorter than 50 ns. On the other side, a valid pulse must be longer than 500 ns so that the

ST10 recognizes a reset command. Between 50 ns and 500 ns, a pulse can either be

filtered or recognized as valid, depending on the operating conditions and process

variations.

For this reason, all minimum durations for the different types of reset events in this section,

should be carefully evaluated taking account of the above requirements.

In particular, for the short hardware reset, where only 4 TCL is specified as the minimum

input reset pulse duration, the operating frequency is a key factor. For example:

●

For a CPU clock of 64 MHz, 4 TCL is 31.25 ns, so it is filtered: In this case, the

minimum becomes the value imposed by the filter (500 ns).

●

For a CPU clock of 4 MHz, 4 TCL is 500 ns: In this case, the minimum value from the

formula (see conditions column in Table 131) is coherent with the limit imposed by the

filter.

Table 131.

Reset event definition

Reset source

Flag

RPD

status

Conditions

Power-on reset

PONR

Low

Power-on

Asynchronous hardware

reset

LHWR

Low

tRSTIN > 500 ns and > Port 0 set-up time

(1)

The RSTIN pulse should be > 500 ns (filter) and > Port 0 set-up time. If Port 0 set-up time is below 500

ns, there is no additional settling time. See Section 20.1 for more details on minimum and reset pulse

duration.

Synchronous long

hardware reset

High

tRSTIN > (1032 + 12) TCL + max (4 TCL, 500 ns)

Synchronous short

hardware reset

SHWR

High

tRSTIN > max(4 TCL, 500 ns)

tRSTIN ≤(1032 + 12) TCL + max (4 TCL, 500ns)

Watchdog timer reset

WDTR

(2)

The RPD pin status has no influence unless a bidirectional reset is activated (BDRSTEN bit in the

SYSCON register). When RPD is low, bidirectional resets on software and watchdog timer reset events

are inhibited (that is, RSTIN is not activated) Refer to Section 20.4, Section 20.5 and Section 20.6).

WDT overflow

Software reset

SWR

(2)

SRST instruction execution

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