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ST10F296 データシート(PDF) 224 Page - STMicroelectronics |
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ST10F296 データシート(HTML) 224 Page - STMicroelectronics |
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224 / 346 page  Obsolete Product(s) - Obsolete Product(s) System reset ST10F296E 224/346 Figure 80. Synchronous short/long hardware reset (EA = 0) 1. RSTIN assertion can be released here. See Section 21.1: Idle mode on page 240 for details on minimum pulse duration. 2. If RPD voltage drops below the threshold voltage (about 2.5 V for 5 V operation) during the reset condition (RSTIN low), an asynchronous reset is entered immediately. 3. Three to eight TCL depending on clock source selection. 4. The RSTIN pin is pulled low if the BDRSTEN bit (of the SYSCON register) was previously set by software. The BDRSTEN bit is cleared after reset. 5. The minimum RSTIN low pulse duration must be longer than 500 ns, to guarantee the pulse is not masked by the internal filter (see Section 21.1: Idle mode on page 240). P0[15:13] Not transparent RSTF P0[12:2] Transparent Not t. P0[1:0] Not t. Not transparent RST 1024 TCL 3..8 TCL(3) (2) V RPD > 2.5 V asynchronous reset not entered 200 mA discharge RPD RSTOUT At this time RSTF is sampled high or low so it is a short or long reset (after filter) RSTIN < 1032 TCL ≤4 TCL(5) (4) ≤12 TCL (1) ≤500 ns ≥ 50 ns ≤500 ns ≥ 50 ns ≤500 ns ≥ 50 ns ALE 8 TCL 8 TCL Not t. Obsolete Product(s) - Obsolete Product(s) |
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