ST10F296 datasheet(307/346 Pages) STMICROELECTRONICS

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Electrical characteristics

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Input leakage and external circuit

The series resistor used to limit the current to a pin (see RL in Figure 99), in combination

with a large source of impedance, can lead to a degradation of the ADC accuracy when

input leakage is present.

Data about maximum input leakage current at each pin is provided in Section 24.5: DC

characteristics. Input leakage is greatest at high operating temperatures and generally

decreases by one half a degree for each 10 °C decrease in temperature.

Considering that one count of a 10-bit ADC is about 5 mV (assuming VAREF = 5 V), an input

leakage of 100 nA acting though an RL = 50 kΩ of external resistance, leads to an error of

exactly one count (5 mV). If the resistance is 100 k

Ω, the error is two counts (10 mV).

Additional leakage due to external clamping diodes must also be taken into account in

computing the total leakage affecting the ADC measurements. Another contribution to the

total leakage is represented by the charge sharing effects with the sampling capacitance.

The sampling capacitance, CS, is essentially a switched capacitance with a frequency equal

to the conversion rate of a single channel (maximum when the fixed channel continuous

conversion mode is selected). It can be seen as a resistive path to ground. For instance,

assuming a conversion rate of 250 kHz and a CS of 4 pF, a resistance of 1 MΩ is obtained

(REQ = 1/fCCS, where fC represents the conversion rate at the considered channel). To

minimize the error induced by the voltage partitioning between this resistance (sampled

voltage on CS) and the sum of RS + RF + RL + RSW + RAD, the external circuit must be

designed to respect the following relation:

Equation 25

Equation 25 places constraints on the external network design, in particular on the resistive

path.

A second aspect of the capacitance network must be considered. Assuming the three

capacitances, CF, CP1 and CP2, are initially charged at the source voltage VA (see

Figure 99), when the sampling phase is started (ADC switch closed), a charge-sharing

phenomena begins (see Figure 100).

Figure 100. Charge sharing timing diagram during sampling phase

Two different transient periods can be distinguished in Figure 100. They are described

below.

() R

⁄

()LSB

VA1

VA2

VCS

Voltage transient on CS

∆V < 0.5 LSB

τ 1 < (RSW + RAD) CS << TS

τ 2 = RL (CS + CP1 + CP2)

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