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ST10F296 データシート(PDF) 312 Page - STMicroelectronics

部品番号 ST10F296
部品情報  High performance 16-bit CPU with DSP functions
PDF  346 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F296 データシート(HTML) 312 Page - STMicroelectronics

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Electrical characteristics
ST10F296E
312/346
Figure 103. Float waveforms
1.
For timing purposes, a port pin is no longer floating when VLOAD changes of ±100 mV occur.
2.
VLOAD begins to float when a 100 mV change from the loaded VOH/VOL level occurs (IOH/IOL = 20 mA).
24.8.2
Definition of internal timing
The internal operation of the ST10F296E is controlled by the internal CPU clock fCPU. Both
edges of the CPU clock can trigger internal (for example, pipeline) or external (for example,
bus cycle) operations.
The specification of the external timing (AC characteristics) depends on the time (TCL)
between two consecutive edges of the CPU clock.
The CPU clock signal can be generated by different mechanisms. The duration of TCL and
its variation (and also the derived external timing) depends on the mechanism used to
generate fCPU.
The fCPU influence must be regarded when calculating the timings for the ST10F296E.
The example for PLL operation shown in Figure 104 refers to a PLL factor of four.
The mechanism used to generate the CPU clock is selected during reset by the logic levels
on pins P0.15-13 (P0H.7-5).
Timing
reference
points
VLOAD + 0.1 V
VLOAD - 0.1 V
VOH - 0.1 V
VOL + 0.1 V
VLOAD
VOL
VOH
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