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STM8S005C6 データシート(PDF) 79 Page - STMicroelectronics

部品番号 STM8S005C6
部品情報  Extended instruction set
PDF  97 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
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STM8S005C6 データシート(HTML) 79 Page - STMicroelectronics

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STM8S005C6 STM8S005K6
Electrical characteristics
84
9.3.10
10-bit ADC characteristics
Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise
specified.
Table 43. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fADC
ADC clock frequency
VDDA = 3 to 5.5 V
1
-
4
MHz
VDDA = 4.5 to 5.5 V
1
-
6
VDDA
Analog supply
-
3
-
5.5
V
VREF+
Positive reference voltage
-
2.75(1)
1.
Data guaranteed by design, not tested in production..
-VDDA
V
VREF-
Negative reference voltage
-
VSSA
-0.5(1)
V
VAIN
Conversion voltage range(2)
2.
During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
-VSSA
-VDDA
V
Devices with external
VREF+/VREF- pins
VREF-
-VREF+
V
CADC
Internal sample and hold
capacitor
--
3
-
pF
tS
(2)
Sampling time
fADC = 4 MHz
0.75
µs
fADC = 6 MHz
0.5
tSTAB
Wakeup time from standby
-
-
7
-
µs
tCONV
Total conversion time (including
sampling time, 10-bit resolution)
fADC = 4 MHz
3.5
µs
fADC = 6 MHz
2.33
µs
-14
1/fADC



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