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DS2148 データシート(PDF) 39 Page - Dallas Semiconductor

部品番号 DS2148
部品情報  5V E1/T1/J1 Line Interface
PDF  75 Pages
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メーカー  DALLAS [Dallas Semiconductor]
ホームページ  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2148 データシート(HTML) 39 Page - Dallas Semiconductor

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DS2148/Q48
39 of 75
RIR2 (09H): RECEIVE INFORMATION REGISTER 2
(MSB)
(LSB)
RL3
RL2
RL1
RL0
N/A
N/A
ARLB
SEC
SYMBOL
POSITION
DESCRIPTION
RL3
(real time)
RIR2.7
Receive Level Bit 3. See Table 7-2.
RL2
(real time)
RIR2.6
Receive Level Bit 2. See Table 7-2.
RL1
(real time)
RIR2.5
Receive Level Bit 1. See Table 7-2.
RL0
(real time)
RIR2.4
Receive Level Bit 0. See Table 7-2.
N/A
RIR2.3
Not Assigned. Could be any value when read.
N/A
RIR2.2
Not Assigned. Could be any value when read.
ARLB
(real time)
RIR2.1
Automatic Remote Loopback Detected. This bit will be set to
a one when the automatic Remote Loopback (RLB) circuitry
has detected the presence of a loop up code for 5 seconds. It
will remain set until the automatic RLB circuitry has detected
the loop down code for 5 seconds. See Section 6 for more
details. This bit will be forced low when the automatic RLB
circuitry is disabled (CCR6.5 = 0).
SEC
(latched)
RIR2.0
One-Second Timer. This bit will be set to a one on one-second
boundaries as timed by the device based on the RCLK. It will
be cleared when read.
RECEIVE LEVEL INDICATION Table 7-2
RL3
RL2
RL1
RL0
Receive Level
(dB)
0
0
0
0
< -2.5
0
0
0
1
-2.5 to -5.0
0
0
1
0
-5.0 to -7.5
0
0
1
1
-7.5 to -10.0
0
1
0
0
-10.0 to -12.5
0
1
0
1
-12.5 to -15.0
0
1
1
0
-15.0 to -17.5
0
1
1
1
-17.5 to -20.0
1
0
0
0
-20.0 to -22.5
1
0
0
1
-22.5 to -25.0
1
0
1
0
-25.0 to -27.5
1
0
1
1
-27.5 to -30.0
1
1
0
0
-30.0 to -32.5
1
1
0
1
-32.5 to -35.0
1
1
1
0
-35.0 to -37.5
1
1
1
1
> -37.5



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