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AS4C8M32S データシート(PDF) 21 Page - Alliance Semiconductor Corporation

部品番号 AS4C8M32S
部品情報  Fully synchronous operation
PDF  55 Pages
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メーカー  ALSC [Alliance Semiconductor Corporation]
ホームページ  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4C8M32S データシート(HTML) 21 Page - Alliance Semiconductor Corporation

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AS4C8M32S
Alliance Memory Confidential
20
Rev. 2.0 May /2014
Table 14. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 3.3V±0.3V, TA = -40~85°C) (Note: 5, 6, 7, 8)
Symbol
A.C. Parameter
-6
-75
Unit Note
Min.
Max.
Min.
Max.
tRC
Row cycle time
(same bank)
60
-
67.5
-
tRCD
RAS# to CAS# delay
(same bank)
18
-
22.5
-
tRP
Precharge to refresh/row activate command
(same bank)
18
-
22.5
-
ns
tRRD
Row activate to row activate delay
(different banks)
12
-
15
-
tRAS
Row activate to precharge time
(same bank)
42
100k
45
100k
tWR
Write recovery time
2
-
2
-
tCK
tCCD
CAS# to CAS# Delay time
1
-
1
-
tCK
Clock cycle time
CL* = 2
9
-
10
-
ns
9
CL* = 3
6
-
7.5
-
tCH
Clock high time
2.5
-
2.5
10
tCL
Clock low time
2.5
-
2.5
-
10
tAC
Access time from CLK
(positive edge)
CL* = 2
-
6
-
6
10
CL* = 3
-
5
-
5.4
tOH
Data output hold time
2
-
2
-
9
tLZ
Data output low impedance
1
-
1
-
tHZ
Data output high impedance
-
5
-
5.4
8
tIS
Data/Address/Control Input set-up time
2
-
2
-
10
tIH
Data/Address/Control Input hold time
1
-
1
-
10
tPDE
Power Down Exit set-up time
tIS+ tCK
-
tIS+ tCK
-
tREFI
Average Refresh Interval Time
-
15.6
-
15.6
s
tDAL
Last data in to active latency
5
-
5
-
tCK
tXSR
Exit Self Refresh to Read Command time
tIS+ tRC
-
tIS+ tRC
-
ns
*
CL is CAS Latency.
Note:
1. Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to
the device.
2. All voltages are referenced to VSS. VIH (Max) = 4.6V for pulse width ≤ 3ns. VIL (Min) = -1.0V for pulse
width ≤ 3ns.
3. These parameters depend on the cycle rate and these values are measured by the cycle rate under the
minimum value of tCK and tRC. Input signals are changed one time during every 2 tCK.
4. These parameters depend on the output loading. Specified values are obtained with the output open.
5. Power-up sequence is described in Note 11.
6. A.C. Test Conditions



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