データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

M95040-DF データシート(PDF) 13 Page - STMicroelectronics

部品番号 M95040-DF
部品情報  Compatible with SPI bus serial interface
PDF  46 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M95040-DF データシート(HTML) 13 Page - STMicroelectronics

Back Button M95040-DF Datasheet HTML 9Page - STMicroelectronics M95040-DF Datasheet HTML 10Page - STMicroelectronics M95040-DF Datasheet HTML 11Page - STMicroelectronics M95040-DF Datasheet HTML 12Page - STMicroelectronics M95040-DF Datasheet HTML 13Page - STMicroelectronics M95040-DF Datasheet HTML 14Page - STMicroelectronics M95040-DF Datasheet HTML 15Page - STMicroelectronics M95040-DF Datasheet HTML 16Page - STMicroelectronics M95040-DF Datasheet HTML 17Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 46 page
background image
DocID6512 Rev 13
13/46
M950x0-W M950x0-R M950x0-DF
Operating features
45
4
Operating features
4.1
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
Normally, the device is kept selected, for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if it is required to reset any processes that had
been in progress.
The Hold condition starts when the Hold (HOLD) signal is driven low at the same time as
Serial Clock (C) already being low (as shown in Figure 5: Hold condition activation).
The Hold condition ends when the Hold (HOLD) signal is driven high at the same time as
Serial Clock (C) already being low.
Figure 5: Hold condition activation also shows what happens if the rising and falling edges
are not timed to coincide with Serial Clock (C) being low.
Figure 5. Hold condition activation
4.2
Status register
Figure 6 shows the position of the Status register in the control logic of the device. This
register contains a number of control bits and status bits, as shown in Table 6: Status
register format and as detailed in Section 6.3: Read Status Register (RDSR).



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com