LRI64 datasheet(11/38 Pages) STMICROELECTRONICS

部品番号	LRI64

部品情報	Memory TAG IC, 64-bit Unique ID with WORM User Area 13.56MHz, ISO15693 and ISO18000-3 Mode 1 Compliant

PDF	38 Pages

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メーカー	STMICROELECTRONICS [STMicroelectronics]

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LRI64

LRI64 TO VCD FRAMES

Response Frames are delimited by a Start of

Frame (SOF) and an End of Frame (EOF) and are

implemented using a code violation mechanism.

The LRI64 supports these in the one subcarrier

mode, at the fast data rate, only.

The VCD is ready to receive a response frame

from the LRI64 before 320.9µs (t1) after having

sent a command frame.

LRI64 SOF

SOF comprises three parts: (see Figure 12.)

–

an unmodulated period of 56.64µs,

–

24 pulses of 423.75kHz (fc/32),

–

a logic 1 which starts with an unmodulated

period of 18.88µs followed by 8 pulses of

423.75kHz.

LRI64 EOF

EOF comprises three parts: (see Figure 13.)

–

a logic 0 which starts with 8 pulses of

423.75kHz followed by an unmodulated

period of 18.88µs.

–

24 pulses of 423.75kHz (fC/32),

–

an unmodulated time of 56.64µs.

Figure 12. Response SOF, using High Data Rate and One Subcarrier

Figure 13. Response EOF, using High Data Rate and One Subcarrier

AI06671B

113.28 µs

37.76 µs

AI06675B

113.28 µs

37.76 µs

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