LTC3900 datasheet(10/12 Pages) LINER

10 / 12 page

LTC3900

3900i

APPLICATIO S I FOR ATIO

Figure 9. VCC Regulator

If the LTC3900 still operates in discontinuous mode with

the calculated resistance value, increase the value of RCS1

to raise the threshold. The resistors RCS1 and RCS2 and the

CS+ pins input capacitance plus the PCB trace capacitance

forms an R-C delay; this slows down the response time of

the comparator. The resistors and CS+ input leakage

currents also create an input offset error.

To minimize this delay and error, do not use resistance

value higher than required and make the PCB trace from

the resistors to the LTC3900 CS+/CS– pins as short as

possible. Add a series resistor, RCS3 with value equal to

parallel sum of RCS1 and RCS2 to the CS– pin and connect

the other end of RCS3 directly to the source of Q4.

SYNC Input

Figure 7 shows the external circuit for the LTC3900 SYNC

input. With a selected type of pulse transformers, the

values of the CSG and RSYNC should be adjusted to obtain

a optimum SYNC pulse amplitude and width. A bigger

capacitor, CSG, generates a higher and wider SYNC pulse.

The peak of this pulse should be much higher than the

typical LTC3900 SYNC threshold of

±1.4V. Amplitudes

greater than

±5V will help to speed up the SYNC compara-

tor and reduce the SYNC to drivers propagation delay. The

pulse width should be wider than 75ns. Overshoot during

the pulse transformer reset interval must be minimized

and kept below the minimum SYNC threshold of

±1V. The

amount of overshoot can be reduced by having a smaller

RSYNC.

VCC Regulator

The VCC supply for the LTC3900 can be generated by peak

rectifying the transformer secondary winding as shown in

Figure 9. The Zener diode DZ sets the output voltage to

(VZ – 0.7V). A resistor, RB (on the order of a few hundred

ohms), in series with the base of QREG may be required to

surpress high frequency oscillations depending on QREG’s

selection.

The LTC3900 has an UVLO detector that pulls the drivers

output low if VCC < 4.1V. The UVLO detector has 0.5V of

hysteresis to prevent chattering.

In a typical forward converter, the secondary-side circuits

have no power until the primary-side controller starts

operating. Since the power for biasing the LTC3900 is

derived from the power transformer T1, the LTC3900 will

initially remain off. During that period (VCC < 4.1V), the

output rectifier MOSFETs Q3 and Q4 will remain off and the

MOSFETs body diodes will conduct. The MOSFETs may

experience very high power dissipation due to a high

voltage drop in the body diodes. To prevent MOSFET

damage, VCC voltage greater than 4.1V should be provided

Figure 7. SYNC Input Circuit

Figure 8. Symmetrical SYNC Drive

RSYNC

470

Ω

T2: COILCRAFT Q4470B

OR PULSE P0926

CSG

220pF

PRIMARY

CONTROLLER

LTC3900

SYNC

3900 F06

RSYNC

470

Ω

LTC3900

SYNC

3900 F07

74HC14

74HC132

470

Ω

220pF

SYNC

PRIMARY

CONTROLLER

3900 F08

MBR0540

SECONDARY

WINDING

0.1

µF

Ω

QREG

BCX55

CVCC

4.7

µF

VCC

7.5V

An alternative method of generating the SYNC pulse is

shown in Figure 8. This circuit produces square SYNC

pulses with amplitude dependent on the logic supply

voltage. The SYNC pulse width can be adjusted with R1

and C1 without affecting the pulse amplitude.

For nonisolated applications, the SYNC input can be driven

directly by a bipolar square pulse. To reduce the propaga-

tion delay, make the positive and negative magnitude of

the square wave much greater than the

±1.4V SYNC

threshold.

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