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STMPE812ABJR データシート(PDF) 41 Page - STMicroelectronics

部品番号 STMPE812ABJR
部品情報  Integrated 4-wire resistive touchscreen controller, pen-down/real-time mode, fullyautonomous
PDF  53 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STMPE812ABJR データシート(HTML) 41 Page - STMicroelectronics

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STMPE812A
GPIO port controller
Doc ID 18225 Rev 4
41/53
12
GPIO port controller
A total of 3 configurable ports are available in the STMPE812A port expander device.
If configured as GPIO input/output, they are controlled by the GPIO registers.
All GPIO registers are named as GPxx, where:
Xxx represents the functional group
The function of each bit is shown in Table 15:
If both GPFE and GPRE are not set, state transition on a GPIO does not cause an interrupt.
On power-up reset, all GPIO are set as input.
Table 14.
GPIO registers
Address
Register
Bit
Type
Reset
Function
0x10
GPIO_SET_PIN
8
R/W
0x00
Set pin state
0x11
GPIO_CLR_PIN
8
R/W
0x00
Clear pin state
0x12
GPIO_MP_STA
8
R/W
0x00
Monitor pin state
0x13
GPIO_DIR
8
R/W
0x00
Falling edge
detection enable
0x14
GPIO_ED
8
R/W
0x00
Rising edge
detection enable
Bit
7
6543210
GPxx
IO-2
RESERVED
IO-1
IO-0
Table 15.
GPIO registers
Register name
Function
GPIO monitor pin state
Reading this bit yields the current state of the bit. Writing has no effect.
GPIO set pin state
Writing ‘1’ to this bit causes the corresponding GPIO to go to ‘1’ state.
Writing ‘0’ to this bit has no effect
Reading this register always yield 0x00
GPIO clear pin state
Writing ‘1’ to this bit causes the corresponding GPIO to go to ‘0’ state.
Writing ‘0’ to this bit has no effect
Reading this register always yield 0x00
GPIO falling edge detection
enable
Writing ‘1’ to this bit allows interrupt generation when there is a falling
edge at the corresponding GPIO
Writing ‘0’ disables the interrupt generation on falling edge detection
GPIO rising edge detection
enable
Writing ‘1’ to this bit allows interrupt generation when there is a rising
edge at the corresponding GPIO
Writing ‘0’ disables the interrupt generation on rising edge detection



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