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TMS29LF040 データシート(PDF) 15 Page - Texas Instruments

部品番号 TMS29LF040
部品情報  524288 BY 8-BIT FLASH MEMORIES
PDF  38 Pages
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メーカー  TI [Texas Instruments]
ホームページ  http://www.ti.com
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TMS29LF040 データシート(HTML) 15 Page - Texas Instruments

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TMS29LF040, TMS29VF040
524288 BY 8-BIT
FLASH MEMORIES
SMJS825D – SEPTEMBER 1995 – REVISED JUNE 1998
15
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251–1443
timing requirements controlled by W (see Figure 4, Figure 7, Figure 9, Figure 11, Figure 13,
Figure 15, and Figure 17)
ALTERNATE
SYMBOL
’29LF040-80
’29LF040-90
’29LF040-10
’29VF040-10
UNIT
SYMBOL
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
tAVAV
Cycle time, write
tc(W)
80
90
100
ns
tWHWH1
Cycle time, programming
operation
tc(W)PR
20
20
20
µs
tWHWH2
Cycle time, sector-erase
operation
2
30
2
30
2
30
s
tWHWH3
Cycle time, chip-erase
operation
14
120
14
120
14
120
s
tWLAX
Hold time, address
th(A)
45
45
45
ns
tWHDX
Hold time, data valid after
W high
th(D)
0
0
0
ns
tWHEH
Hold time, E
th(E)
0
0
0
ns
tWHWL
Pulse duration, W high
tw(WH)
20
20
20
ns
tWLWH1
Pulse duration, W low
tw(WL)
35
45
45
ns
tWLWH2
Pulse duration, W low
(see Note 7)
100
100
100
µs
tWLWH3
Pulse duration, W low
(see Note 8)
10
10
10
ms
tGHWL
Recovery time, read
before write
trec(R)
0
0
0
ns
tAVWL
Setup time, address
tsu(A)
0
0
0
ns
tDVWH
Setup time, data
tsu(D)
35
45
45
ns
tAVGH
Setup time, A0 and A6
low and A1 high to G high
(see Note 7)
0
0
0
ns
tAVGEH
Setup time, A0 low and
A1 high to G and E high
(see Note 8)
0
0
0
ns
tELWL
Setup time, E
tsu(E)
0
0
0
ns
tGHWH
Setup time, G
0
0
0
ns
tVCEL
Setup time, VCC
50
50
50
µs
tEHVWL
Setup time, E VID to W
(see Note 8)
4
4
4
µs
tGHVWL
Setup time, G VID to W
(see Notes 7 and 8)
4
4
4
µs
tHVT
Transition time, VID (see
Notes 7 and 8)
4
4
4
µs
NOTES:
7. Sector-protect timing (see Figure 15)
8. Sector-unprotect timing (see Figure 17)



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