LT5516

11

5516f

APPLICATIO S I FOR ATIO

11

10

LO

J2

T2

LDB31900M20C-416

5516 F06

200

Ω

2.44V

2.44V

L4

27nH

6

2

4

1

3

C2

1nF

15

16

5pF

+

–

5516 F07

13

14

5pF

+

–

60

Ω

60

Ω

60

Ω

60

Ω

Figure 6. LO Input Equivalent Circuit with External Matching

Figure 7. I/Q Output Equivalent Circuit

PACKAGE DESCRIPTIO

UF Package

16-Lead Plastic QFN (4mm

× 4mm)

(Reference LTC DWG # 05-08-1692)

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-

tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

4.00

± 0.10

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGC)

2. ALL DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

4. EXPOSED PAD SHALL BE SOLDER PLATED

PIN 1

TOP MARK

0.55

± 0.20

16

15

1

2

BOTTOM VIEW—EXPOSED PAD

2.15

± 0.10

(4-SIDES)

0.75

± 0.05

R = 0.115

TYP

0.30

± 0.05

0.65 BSC

0.200 REF

0.00 – 0.05

(UF) QFN 0802

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.72

±0.05

0.30

±0.05

0.65 BSC

2.15

± 0.05

(4 SIDES)

2.90

± 0.05

4.35

± 0.05

PACKAGE OUTLINE