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AD7183 データシート(PDF) 34 Page - Analog Devices |
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AD7183 データシート(HTML) 34 Page - Analog Devices |
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34 / 40 page ![]() REV. 0 –34– ADV7183 Table XLVIII. Polarity Register (Subaddress 37) Bit Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register Setting PCLK 1 0 Active High 1 Active Low PFF 2 0 Active High 1 Active Low PDV 3 0 Active High 1 Active Low PF 4 0 Active High 1 Active Low PLLCR 5 0 Active High 1 Active Low PVS 6 0 Active High 1 Active Low PHVR 7 0 Active High 1 Active Low PHS 8 0 Active High 1 Active Low NOTES 1Sets the polarity of LLC, LLC2, and QClk. 2Sets the polarity of HFF, AEF, and AFF. 3Sets the polarity for Data Field. 4Sets the field sync polarity. 5Sets the LLCREF polarity. 6Sets the VSync polarity. 7Sets the HREF and VREF sync polarities. 8Sets HSync Polarity. |
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