Pin

No.

Pin name

Supply class

Pin type

Rst func

Rst level

Description

30 VSEAL

PWR

Sealring supply

41 VSSA1

GND

Analog ground VSSA

45 VSSA2

GND

Analog ground VSSA

40 VSSPX1

GND

Pixel analog ground VSSPX

46 VSSPX2

GND

Pixel analog ground VSSPX

50 VSSLED

GND

Table 8 cont.: Pin list

Notes:

1

DIO pin is configured as input with internal pull-down resistor enabled during RESET = 0 (active), only. As soon as RESET is driven to 1,

pins stay in that state for another 4x osc_clk periods (see chapter 5.3.3., Strap pins), then the pin is configured as output, finally the in-

ternal pull-down resistor is disabled. From this moment on, the pin can be used for normal output function.

2

VSSLED is the dedicated, isolated GND pin for the LED/LD return-current from external circuitry. It must be connected to PCB GND

plane together with the other VSSA GND pins.

3

LED output can be used to drive an external amplifier with an addition of a pull-up resistor. The voltages at LED output and LEDFB input

pins must not exceed values in Table 1: Operating conditions and electrical characteristics.

LED2 output is a push-pull driver for delivering symmetric rise/fall times to the external LED driver circuit. LED2 is internally connected to

VDDIO/VSSIO supplies. During integration time, all TCMI pins are silent except for DCLK. As a result, LED2 pin will not pick up switch -

ing noise from all other TCMI pins but the layout has to take care of the DCLK line.

When the TCMI interface is slowed down by setting DCLK <= 5MHz, data-out phase of the last two rows may overlap with the next

frame's integration time as another noise source for very short integration times (<100 µs). This can be avoided by

SEQ_Control.pixel_seq_wait_row_done_en = 1 (default) with a small reduction on the frame rate.

LED and LED2 must not be used simultaneously for driving LED circuits on the PCB. They exhibit different insertion delays and may

cause unpredicted distance offset/measurement results.

4

RESET pin has a 600kΩ (typical) internal pull-down resistor. Therefore, this pin can be safely connected to a standard GPIO of a CPU

which is initially high-Z or open-drain during power up sequence. Once the SW takes control, it can program this GPIO as output and

drive 1 to release the RESET. The internal pull-down can be override by and external 10kΩ pull-up and a series capacitor to build a sim-

ple delayed power-on reset for evaluation/qualification purposes.

5

R1 and R2 in the schematics are given only for indicative purposes and must be re-calculated according to the total capacitive load of all

'Pin type' in Table 8 defines the following:

■ DI: Digital Input

■ DO: Digital Output

■ DIO: Digital Input/Output (bidirectional)

■ DIOD: Digital Input/Output (bidirectional), open-Drain

■ AI: Analog Input

■ AO: Analog Output

■ AOD: Analog Output, open-Drain

■ PWR: Supply

■ GND: Ground

'Rst. Func.' in Table 8 defines the function of IO pins during reset:

■ I: Input

■ PU: internal Pull-Up

■ PD: internal Pull-Down

■ IPD: Input with internal Pull-Down

'Rst. Level' in Table 8 defines the level of the IO pins during/after

reset (chapter 5.3.)

© 2017 ESPROS Photonics Corporation

Characteristics subject to change without notice

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Datasheet_epc660-V1.09

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