MIC2186

Micrel

MIC2186

2

July 2002

Pin Description

Pin Number

Pin Name

Pin Function

1

VINA

Input voltage to control circuitry (2.9V to 14V).

2

SKIP

SKIP (Input): Regulator operates in PWM mode (no pulse skipping) when

pin is pulled low, and skip mode when raised to Vdd. There is no automatic

switching between PWM and skip mode available on this device.

3

SS

Soft start reduces the inrush current and delays and slows the output voltage

rise time. A 5

µA current source will charge the capacitor up to Vdd.

4

COMP

Compensation (Output): Internal error amplifier output. Connect to a

capacitor or series RC network to compensate the regulator’s control loop.

5

SGND

Small signal ground: must be routed separately from other grounds to the (-)

terminal of Cout.

6

FB

Feedback Input - regulates FB to 1.245V.

7

EN/UVLO

Enable/Undervoltage Lockout (input): A low level on this pin will power down

the device, reducing the quiescent current to under 0.5

µA. This pin has two

separate thresholds, below 1.5V the output switching is disabled, and below

0.9V the device is forced into a complete micropower shutdown. The 1.5V

threshold functions as an accurate undervoltage lockout (UVLO) with 135mV

hysteresis.

8

VREF

The 1.245V reference is available on this pin. A 0.1

µF capacitor should be

connected form this pin to SGnd.

9

CSH

The (+) input to the current limit comparator. A built in offset of 100mV

between CSH and SGnd in conjunction with the current sense resistor sets

the current limit threshold level. This is also the (+) input to the current

amplifier.

10

VDD

3V internal linear-regulator output. Vdd is also the supply voltage bus for the

chip. Bypass to SGND with 1

µF. Maximum source current is 0.5mA.

11

SYNC

Frequency Synchronization (Input): Connect an external clock signal to

synchronize the oscillator. Leading edge of signal above 1.5V starts switch-

ing cycle. Connect to SGND if not used.

12

PGND

MOSFET driver power ground, connects to the bottom of the current sense

resistor and the (–) terminal of C

13

HIDC

High Duty Cycle. Sets duty cycle and frequency along with Freq/2. Logic

HIGH sets 85% maximum duty cycle. Logic LOW sets 50% maximum duty

cycle. See applications section for more information.

14

OUTN

High current drive for N channel MOSFET. Voltage swing is from ground to

V

15

FREQ/2

Sets duty cycle and frequency along with HiDC. See applications section for

more information.

16

VINP

Power input voltage to the gate drive circuitry (2.9V to 14V). This pin is

normally connected to the output voltage.

Pin Configuration

1

VINA

SKIP

SS

COMP

SGND

FB

EN/UVLO

VREF

16 VINP

FREQ/2

OUTN

HIDC

PGND

SYNC

VDD

CSH

15

14

13

12

11

10

9

2

3

4

5

6

7

8

16-pin Narrow Body SOP (M)

16-pin QSOP (QS)