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PS8545 06/20/01

ProductDescription

PI6CV855PLLclockdeviceisdevelopedforSSTL_DDRSDRAM

The device is a zero delay buffer that distributes a differential clock

input pair (CLK, CLK) to five differential pairs of clock outputs

(Y[0:4], Y[0:4]) and one differential pair feedback clock outputs

(FBOUT, FBOUT). The clock outputs are controlled by the input

clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), and the

PLL is turned off and bypassed for test purposes.

When the input frequency falls below a suggested detection fre-

quency that is below the operating frequency of the PLL, the device

willenteralowpowermode.Inlowpowermode,PLListurnedOFF,

Y[0:4] and Y[0:4] outputs are 3-stated.

The PI6CV855 is able to track Spread Spectrum Clocking to reduce

EMI.

ProductFeatures

• PLLclockdistributionoptimizedforSSTL_2DDRSDRAM

applications.

• Distributes one differential clock input pair to five differential

clock output pairs.

• Inputs(CLK,CLK)and(FBIN,FBIN): SSTL_2

• Outputs (Yx,Yx),(FBOUT,FBOUT): SSTL_2

• External feedback pins (FBIN,FBIN) are used to

synchronize the outputs to the clock input.

• AvailablePackage:

–Plastic28-pinTSSOP

BlockDiagram

PI6CV855

PLL Clock Driver for 2.5V

SSTL 2 DDR SDRAM Memory

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Y0

Y0

Y1

FBIN

FBIN

CLK

CLK

PLL

Y1

Y2

Y2

Y3

Y3

Y4

Y4

Logic

and

Test Ciruit

VDDQ

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

15

16

Y4

FBIN

VDDQ

GND

Y3

Y3

GND

FBIN

FBOUT

FBOUT

VDDQ

Y4

GND

Y0

Y0

CLK

CLK

Y1

GND

VDDQ

VDDQ

A GND

Y2

Y2

Y1

GND

AV DD

28-Pin

L

PinConfiguration