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R5F104LEG データシート(PDF) 97 Page - Renesas Technology Corp

部品番号 R5F104LEG
部品情報  True Low Power Platform
PDF  213 Pages
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メーカー  RENESAS [Renesas Technology Corp]
ホームページ  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F104LEG データシート(HTML) 97 Page - Renesas Technology Corp

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RL78/G14
2. ELECTRICAL SPECIFICATIONS (TA = -40 to +85
°C)
R01DS0053EJ0330 Rev. 3.30
Page 97 of 208
Aug 12, 2016
UART mode connection diagram (during communication at different potential)
UART mode bit width (during communication at different potential) (reference)
Remark 1.
Rb[
Ω]: Communication line (TxDq) pull-up resistance,
Cb[F]: Communication line (TxDq) load capacitance, Vb[V]: Communication line voltage
Remark 2.
q: UART number (q = 0 to 3), g: PIM and POM number (g = 0, 1, 5, 14)
Remark 3.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10 to 13))
Remark 4.
UART2 cannot communicate at different potential when bit 1 (PIOR01) of peripheral I/O redirection register 0 (PIOR0) is
1.
RL78 microcontroller
TxDq
RxDq
User’s device
Rx
Tx
Vb
Rb
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
Baud rate error tolerance
High-bit width
Low-bit width
1/Transfer rate
TxDq
RxDq



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