W77LE58 datasheet(21/82 Pages) ETC2

21 / 82 page

W77LE58/W77L058A

Publication Release Date: April 17, 20067

- 21 -

Revision A7

XTUP: Crystal Oscillator Warm-up Status. when set, this bit indicates CPU has detected clock to be

ready. Each time the crystal oscillator is restarted by exit from power down mode or the XTOFF bit

is set, hardware will clear this bit. This bit is set to 1 after a power-on reset. When this bit is

cleared, it prevents software from setting the XT/ RG bit to enable CPU operation from crystal

oscillator.

SPTA1: Serial Port 1 Transmit Activity. This bit is set during serial port 1 is currently transmitting data.

It is cleared when TI_1 bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1

will be ignored when this bit is set to 1 and SWB = 1.

SPRA1: Serial Port 1 Receive Activity. This bit is set during serial port 1 is currently receiving a data. It is

cleared when RI_1 bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1 will

be ignored when this bit is set to 1 and SWB = 1.

SPTA0: Serial Port 0 Transmit Activity. This bit is set during serial port 0 is currently transmitting data.

It is cleared when TI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1

will be ignored when this bit is set to 1 and SWB = 1.

SPRA0: Serial Port 0 Receive Activity. This bit is set during serial port 0 is currently receiving a data. It

is cleared when RI bit is set by hardware. Changing the Clock Divide Control bits CD0, CD1 will

be ignored when this bit is set to 1 and SWB = 1.

Timed Access

Bit:

TA.7

TA.6

TA.5

TA.4

TA.3

TA.2

TA.1

TA.0

Mnemonic: TA

Address: C7h

TA: The Timed Access register controls the access to protected bits. To access protected bits, the user

must first write AAH to the TA. This must be immediately followed by a write of 55H to TA.

Now a window is opened in the protected bits for three machine cycles, during which the user can

write to these bits.

Timer 2 Control

Bit:

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C T

/ 2

CP RL

Mnemonic: T2CON

Address: C8h

TF2:

Timer 2 overflow flag: This bit is set when Timer 2 overflows. It is also set when the count is

equal to the capture register in down count mode. It can be set only if RCLK and TCLK are both

0. It is cleared only by software. Software can also set or clear this bit.

EXF2: Timer 2 External Flag: A negative transition on the T2EX pin (P1.1) or timer 2 overflow will cause

this flag to set based on the

CP RL

2 , EXEN2 and DCEN bits. If set by a negative transition,

this flag must be cleared by software. Setting this bit in software or detection of a negative

transition on T2EX pin will force a timer interrupt if enabled.

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