Production Data

WM8775

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PD, Rev 4.4, October 2008

21

2-WIRE SERIAL CONTROL MODE

The WM8775 supports software control via a 2-wire serial bus. Many devices can be controlled by

the same bus, and each device has a unique 7-bit address (this is not the same as the 7-bit address

of each register in the WM8775).

The WM8775 operates as a slave device only. The controller indicates the start of data transfer with

a high to low transition on DI while CL remains high. This indicates that a device address and data

will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits

on DI (7-bit address + Read/Write bit, MSB first). If the device address received matches the address

of the WM8775 and the R/W bit is ‘0’, indicating a write, then the WM8775 responds by pulling DI low

on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’, the WM8775

returns to the idle condition and wait for a new start condition and valid address.

Once the WM8775 has acknowledged a correct address, the controller sends the first byte of control

data (B15 to B8, i.e. the WM8775 register address plus the first bit of register data). The WM8775

then acknowledges the first data byte by pulling DI low for one clock pulse. The controller then sends

the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8775

acknowledges again by pulling DI low.

The transfer of data is complete when there is a low to high transition on DI while CL is high. After

receiving a complete address and data sequence the WM8775 returns to the idle state and waits for

another start condition. If a start or stop condition is detected out of sequence at any point during

data transfer (i.e. DI changes while CL is high), the device jumps to the idle condition.

Figure 21 2-Wire Serial Interface

1.

B[15:9] are Control Address Bits

2.

B[8:0] are Control Data Bits

The WM8775 has two possible device addresses, which can be selected using the CE pin.

CE STATE

DEVICE ADDRESS

Low

0011010 (0 x 34h)

High

0011011 (0 x 36h)

Table 10 2-Wire MPU Interface Address Selection

CONTROL INTERFACE REGISTERS

DIGITAL AUDIO INTERFACE CONTROL REGISTER

Interface format is selected via the FMT[1:0] register bits:

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R11(0Bh)

0001011

ADC Interface Control

1:0

ADCFMT

[1:0]

10

Interface format Select

00 : right justified mode

01: left justified mode

10: I

11: DSP mode A or B

In left justified, right justified or I2S modes, the LRP register bit controls the polarity of ADCLRC. If

this bit is set high, the expected polarity of ADCLRC will be the opposite of that shown Figure 13,

Figure 14 and Figure 15. Note that if this feature is used as a means of swapping the left and right

channels, a 1 sample phase difference will be introduced. In DSP modes, the LRP register bit is used

to select between modes A and B.